Well voltage control after an erase operation in non-volatile memory transistors is important for preventing latchup, a condition that prevents useful operation. Generally, latchup occurs due to the presence of parasitic PN junctions, particularly when the junctions form parasitic NPN and PNP bipolar transistors. Typically a parasitic transistor is a vertical transistor formed in subsurface wells. When two parasitic transistors interact, the second one often a lateral transistor, latchup occurs. An anti-latchup invention is described in U.S. Pat. No. 6,549,465 to Y. Hirano et al. In the patent, a well voltage setting circuit has a P-MOS transistor for applying an erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to a reference voltage during write and read. The first N-MOS transistor has a driving capacity set to about 1/50 of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage is long enough to prevent occurrence of local latchup during erase.
In flash memory arrays, the channel clearing operation after a flash erase has been known to employ a special discharge circuit. Such a discharge circuit is described in published U.S. Patent Application US2004/0184321 and U.S. Pat. No. 6,714,458, both to S. Gualandri et al. These documents describe an erase discharge circuit in a flash that is coupled to an array source and a P-well bias signal and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
In memory devices having a P-well within a deep N-well, the channel clearing operation after an erase can present a special challenge. For example, see U.S. Pat. No. 6,667,910 to Abedifard et al. This patent describes a flash memory device in which an erase voltage is applied to a well containing flash memory transistors. The well is then discharged toward ground, first by one discharge circuit which discharges the well until the voltage on the well is lower than a snap-back characteristic of a transistor employed in another well discharge circuit. After the well voltage is below the snap-back characteristic of the transistor, the well is discharged by the other discharge circuit.
The existence of a subsurface parasitic p-n junction in double well devices gives rise to special concerns. Forward bias on a vertical parasitic junction can cause device latchup. On the other hand, channel clearing voltages creating forward bias conditions are needed after erase pulses. An object of the invention is to devise a channel clearing bias scheme after an erase pulse which avoids forward bias conditions in parasitic p-n junctions formed by vertical subsurface wells.